1. Field of the Invention
The present invention relates to a dither circuit for a quantizer, and more particularly, to a dither circuit correcting quantization error generated in an analog digital converter (ADC).
2. Description of Related Art
In order to describe the background of the present invention, characteristic of an ADC without dither will be described with taking a ΔΣ (delta sigma) type ADC as an example. FIG. 6 is a configuration diagram of a first-order ΔΣ (delta sigma) ADC without dither signal. This first-order ΔΣADC functions as follows.
When a sampling clock ck is in active state, switches SWain and SWsam are closed and charges sampling analog input signal Vain are stored in an input capacitor C1. Next, when an inverting sampling clock ckb is in active state, switches SWdac and SWint are closed, and charges are transmitted to an integral capacitor C2 according to a feedback reference signal Vr. Then integration is performed in the C2 to change an integrator output Vout. The integrator output Vout is input to a comparator 3 which functions as a quantizer. A quantization output PDM, which is the output from the comparator 3, is delayed by one clock cycle by a delay device 4 and is input to a 1-bit digital analog converter (DAC) 6. The DAC 6 outputs a feedback reference signal Vr. The level of the feedback reference signal Vr has two values of Vrp and Vrn, and the level is determined to be Vrp or Vrn according to the value obtained by examining the previous integration result made by the comparator 3.
A decimation filter 5 obtains the quantization output PDM and removes high side out-of-band noise that is shaped by a delta sigma modulator 10. Then the decimation filter 5 thins out and changes the data output rate to a desired one to output the digital signal output Dout.
FIG. 7 shows output characteristics of the ΔΣ type ADC when an analog input signal is in the vicinity of zero. As shown in FIG. 7, there is a region where the digital output signal outputs constant value. This is because some loss is caused in the integrator. The loss is caused mainly because gain of an operational amplifier forming the integrator has limit, leak current is generated in the capacitor or the switch, or the integrator is not in an ideal state due to existence of parasitic element and soon. Due to this loss, the feedback reference signal is in a stationary state where the feedback reference signal repeats positive side and negative side when the analog input signal is in the vicinity of zero, and the digital output signal has constant value. Therefore, as shown in FIG. 8, the error is also increased when the analog input signal is in the vicinity of zero.
In order to improve this characteristic degradation, the stationary state where the feedback reference signal repeats positive side and negative side is needed to be avoided when the analog input signal is in the vicinity of zero. The process for adding the dither signals is typically used to achieve this object.
A conventional example of the first-order ΔΣ type ADC having a single square wave dither circuit is disclosed in Japanese Unexamined Patent Application Publication No. 2002-100992. FIG. 9 shows a configuration of the ΔΣ type ADC disclosed in Japanese Unexamined Patent Application Publication No. 2002-100992. With reference to FIG. 9, the ΔΣ type ADC includes a dither circuit 1, a switched capacitor type integrator 2, a quantizer 3 made of a comparator, a delay device 4 made of a flip-flop, a decimation filter 5, and a 1-bit DAC 6. FIG. 10 shows configurations of the dither circuit 1 of the ΔΣ type ADC and the 1-bit DAC shown in FIG. 9, and switched capacitors transmitting charges proportional to signal potentials generated at the dither circuit and the 1-bit DAC to an integral capacitor of the integrator 2.
Referring to FIG. 10, the 1-bit DAC 6 includes a switching device 31 controlled by an output Sd of the delay device 4. The switching device 31 outputs reference voltages V1 and V4 generated at the resistors 39 to 43 that are connected in series as a positive side Vrp=V1 and negative side Vrn=V4 of the feedback reference signal Vr, respectively.
The dither circuit 1 includes a switching device 37 controlled by signal obtained by dividing the frequency of sampling clock fs by n using a frequency divider. The frequency dividing ratio of the frequency divider is set so that the cycle of the dither signals becomes more than ⅛ of the output cycle of the decimation filter 5. The switching device 37 switches reference voltages V2 and V3 generated at the resistors 39 to 43 that are connected in series to output the square wave dither whose amplitude is V2-V3. A switched capacitor circuit includes switches 32 and 34 that function at a first timing, switches 35 and 36 that function at a second timing, and a capacitor 33. When the switches 35 and 36 are closed and the switches 32 and 34 are opened, potentials of both ends of the capacitor 33 are made ground potential. When the switches 35 and 36 are opened and the switches 32 and 34 are closed, the dither Vd is output to the input of the integrator 2 which is an adding point. There is a description in Japanese Unexamined Patent Application Publication No. 2002-100992 that the arbitrary waveform can be used as the dither such as delta wave or sawtooth wave although specific example is not shown in this patent.
In the ADC disclosed in U.S. Pat. No. 5,940,138, two square wave dithers having different frequencies and amplitudes are added to the analog video input signal. FIG. 11 shows a configuration of the ADC of U.S. Pat. No. 5,940,138, and FIG. 12 shows the dither waveform thereof. Referring to FIGS. 11 and 12, the dither is generated from the square wave having frequencies of ½ and ¼ of the sampling clock CLK obtained by dividing frequency of the sampling clock CLK using flip-flops 803B and 803C. The two square waves having frequencies of ½ and ¼ are added to the analog video input signal DATA output from a buffer amplifier 805 as the dither of the amplitude of ½ LSB P-P and ¼ LSB P-P by an adding device which includes weighted resistors R, 512R, and 1024R. Note that exclusive OR operation is performed on the signal obtained by dividing frequency of horizontal synchronizing signal H by 2 and the square wave having frequency of ½ of the sampling clock CLK at EX-OR 804A. Exclusive OR operation is also performed on the signal obtained by dividing frequency of horizontal synchronizing signal H by 2 and the square wave having frequency of ¼ of the sampling clock CLK at EX-OR 804B. After these exclusive OR operations, these signals are added to the adding device. Therefore, the ADC has a configuration where the polarity of the dither is inverted for each one horizontal line.
In the conventional dither using the single square wave as disclosed in Japanese Unexamined Patent Application Publication No. 2002-100992, there is an area where the digital output signal becomes constant as in the case without the dither when there is not so much difference between amplitude of the square wave and the analog input signal Vain. As shown in FIG. 13, characteristic improvement cannot be fully achieved in the area where there is not so much difference between the amplitude Vd of the square wave dither signals and the analog input signal Vain. Further, a voltage-dividing resistor for generating the potential having an intermediate level to determine the amplitude level of the dither is needed, which increases circuit size. Further, the DAC for generating arbitrary waveform is also needed when the arbitrary waveform (delta wave or sawtooth wave) is used in the dither, which increases circuit size.
In the conventional example disclosed in U.S. Pat. No. 5,940,138, the resistor that is 512 times or 1024 times larger than the resistor for analog signal input is needed to determine the amplitude of the dither, which increases the circuit size. In a small amplitude where the dither amplitude is 1/512 or 1/1024 of the analog signal input range, the phenomena where the digital output signal becomes constant when the analog input signal Vain is in the vicinity of zero cannot be improved.